A 3.3 mW 12 MS/s 10b pipelined ADC in 90 nm digital CMOS

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外文摘要：A 10b pipelined ADC has been realized in a digital 90 nm CMOS technology using techniques such as switched opamps and switched-input buffers。 Measurements show that this ADC samples at 12 MS/s achieving a peak SNDR of 52。6 dB using a 1。2 V supply。 It consumes 3。3 mW and occupies 0。3 mm/sup 2/ core area。

外文关键词：

CMOS digital integrated circuitsanalogue-digital conversionbuffer circuitsintegrated circuit designintegrated circuit measurementlow-power electronicsoperational amplifiersswitched networks1.2 V10 bit3.3 mW90 nmADC sampling ratecore areadig

作者：

R. Wang、K. Martin、D. Johns、G. Burra

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作者单位：

Univ. of Toronto, Ont., Canada

会议母体文献：

Solid-State Circuits Conference, 2005. Digest of Technical Papers. ISSCC. 2005 IEEE International

页码：

P.278-279