Design and verification based on assertions: some statistics

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原文链接

NETL
IEEE

外文摘要：Usually， the assertion based verification (ABV) is used for the formal verification of digital design。 In this work， we show that it can be used also for the code implementation in a hardware description language (HDL)， saving time and improving the whole design process。 Property specification language (PSL) was used for the written of assertions for a specific circuit。 Finally， a set of properties for finite states machines (FSM) was established。

外文关键词：

finite state machinesformal specificationformal verificationhardware description languagesassertion based verificationcode implementationdigital designfinite state machinesformal verificationhardware description languageproperty specification l

作者：

J. Cortez、D. Torres

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作者单位：

Dept. of Electr. Eng., CINVESTAV-IPN, Guadalajara, Mexico

会议名称：

Electrical and Electronics Engineering, 2005 2nd International Conference on

会议母体文献：

Electrical and Electronics Engineering, 2005 2nd International Conference on

页码：

P.132-135

DOI：

10.1109/ICEEE.2005.1529590