Implementation of precise exception in a 5-stage pipeline embedded processor

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原文链接

NETL
IEEE

外文摘要：An exception is precise if the saved processor state corresponds with the sequential model of program execution where one instruction completes before the next begins。 In a pipelined processor， precise exception is difficult to achieve because an instruction must pass several stages before it modifies the processor's state and many instructions are simultaneously being processed in the different phases of the execution。 In this paper， an approach is provided to implement the 5-stage pipeline RISC processor precise exception in details。

外文关键词：

embedded systemspipeline processinginstruction setsreduced instruction set computing5-stage pipeline embedded processorsequential modelprogram executionpipelined processorprocessors state5-stage pipeline RISC processorreduced instruction set computing

作者：

Liu Zhenyu、Qi Jiayue

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作者单位：

Inst. of Microelectron., Tsinghua Univ., Beijing, China

会议母体文献：

ASIC, 2003. Proceedings. 5th International Conference on

页码：

p.447-451

出版时间：

2003

DOI：

10.1109/ICASIC.2003.1277582