Automatic formal verification for scheduled VLIW code

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原文链接

NETL

外文摘要：VLIW processors are attractive for many embedded applications， but VLIW code scheduling， whether by hand or by compiler， is extremely challenging。 In this paper， we extend previous work on automated verification of low-level software to handle the complexity of modern， aggressive VLIW designs， e。g。， the exposed parallelism， pipelining， and resource constraints。 We implement these ideas into a prototype tool for verifying short sequences of assembly code for TI's C62x family of VLIW DSPs， and demonstrate the effectiveness of the tool in quickly verifying， or finding bugs in， two difficult-to-analyze code segments。

外文关键词：

theory of equality with uninterpreted functions

作者：

Xiushan Feng、Alan J. Hu

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作者单位：

University of British Columbia

会议名称：

Joint conference on Languages, compilers and tools for embedded systems

会议地点：

Berlin(DE)

会议母体文献：

Proceedings of the joint conference on Languages, compilers and tools for embedded systems

页码：

P.85-92

出版时间：

2002

DOI：

10.1145/513829.513844