首页|The design and implementation of Signal Integrity test vector generation based on JTAG
The design and implementation of Signal Integrity test vector generation based on JTAG
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With intensive study on IEEE std1149。1， and the basic idea of HTF(Half Transition) Fault Mode， an architecture for SI(Signal Integrity) test vector based on extended JTAG is designed and realized。 The implementation of the idea is that， The advantage of the new instruction is that on the base of fully complied with IEEE1149。1 standard， it have been added to extend the function of boundary-scan architecture and provide the support to SI testing。
BSCHTFIEEE1149.1PGBSCSI
Yan Xuelong、Hu Hejuan、Li Haihui
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Sch. of Electron. Eng., GUET, Guilin, China
Guilin(CN)
International Conference on Intelligent Computing and Integrated Systems
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