FPGA design and implementation of a matrix multiplier based accelerator for 3D EKF SLAM

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外文摘要：In hw/sw co-design FPGAs are being used in order to accelerate existing solutions so they meet real-time constraints。 As they consume less power than a standard microprocessor and provide powerful parallel data processing capabilities， they remain a highly optimizable tool and object of research within an embedded system。 In this paper we present an efficient architecture for matrix multiplication accelerator conceived as a systolic array co-processor to IBM's PPC440 processor on Virtex5 XC5VFX70T FPGA。 Our design is afterwards synthesized and wired as a large-scale matrix multiplier required for an embedded version of a visual Simultaneous Localization and Mapping (SLAM) algorithm based on Extended Kaiman Filter (EKF)。 This algorithm is implemented entirely as a System On a programmable Chip (SoC) design on the FPGA; an EKF epoch is executed at least 7。3 times faster than the pure software implementation， maintaining and correcting 20 points in the map。 This optimization permits an EKF block throughput to be increased from 6。07Hz to 44。39Hz， which exceeds our real-time constraint of 30Hz。

外文关键词：

Kalman filtersSLAM (robots)control engineering computingembedded systemsfield programmable gate arrayshardware-software codesignintegrated circuit designlogic designmatrix multiplicationmicroprocessor chipsnonlinear filtersparallel processingsystem-on-chipsystolic arrays3D EKF SLAMEKF block throughputEKF epochFPGA designIBM PPC440 processorSLAM algorithmSoC designVirtex5 XC5VFX70T FPGAembedded systemextended Kalman filterhw/sw codesignlarge-scale matrix multipliermatrix multiplication acceleratormatrix multiplier based acceleratormicroprocessoroptimizationparallel data processing capabilityreal-time constraintsoftware implementationsystem on a programmable chipsystolic array coprocessorvisual simultaneous localization and mapping algorithmArraysEquationsField programmable gate arraysIP networksSimultaneous localization and mappingVisualization

作者：

Tertei, Daniel Tortei、Piat, Jonathan、Devy, Michel

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作者单位：

LAAS, Toulouse, France

会议名称：

International Conference on Reconfigurable Computing and FPGAs

会议地点：

Cancun(MX)

会议母体文献：

2014 International Conference on Reconfigurable Computing and FPGAs

页码：

1-6

出版时间：

2014

DOI：

10.1109/ReConFig.2014.7032523