Half-Precision Floating-Point Multiplier IP Core Based on 130 Nm CMOS ASIC Technology

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原文链接

NETL
IEEE

外文摘要：Internet of things applications demand reusable modular designs with low-power consumption。 Furthermore， many emerging applications， such as image recognition using machine learning， are low-accuracy tolerant。 For these applications， the IEEE-754 half-precision arithmetic is becoming a relevant option for low-power， low-computational cost designs。 This article presents a half-precision floating-point multiplier。 It is implemented on 130 nm CMOS ASIC technology。 The proposed multiplier IP core exhibits low-power consumption， small silicon area， and its accuracy is IEEE-754 compliant。

外文关键词：

Computer architectureHardwareStandardsSiliconPower demandMathematical modelDelays

作者：

Cuauhtémoc R. Aguilera-Galicia、Omar Longoria-Gandara、Luis Pizano-Escalante

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作者单位：

Department of Electronics, ITESO-The Jesuit University of Guadalajara, Systems and Informatics, Tlaquepaque, Mexico

Department of Electroni

会议名称：

IEEE Latin-American Conference on Communications

会议地点：

Guadalajara(MX)

会议母体文献：

2018 IEEE 10th Latin-American Conference on Communications

页码：

1-5

出版时间：

2018

DOI：

10.1109/LATINCOM.2018.8613231