查看更多>>摘要：Transistor characteristics in advanced technology nodes are strongly impacted by devices design and process integration choices. Variation in the layout and pattern configuration in close proximity to the device often causes undesirable sensitivities known as Local Layout Effects (LLEs). One of the sensitivities is related to carrier mobility dependence on mechanical stress, modulated by device design and local/ global environment. In this paper we investigate the impact of stress, developed during FinFET device fabrication, on electrical characteristics of transistors manufactured in 7nm silicon FinFET technology. Two sources of stress modulation are studied: (i) active region isolation (Diffusion Break) (ii) Metal Gate extension outside of the fins of the transistor. A 3D TCAD process model of a FinFET device was created and calibrated using electrical characteristics measured on foundry fabricated silicon wafers. The model was then applied to simulate mechanical stress in transistors with various design attributes for Diffusion Breaks (Single vs. Double Diffusion Break) and Gate Cuts, following by modeling of electrical characteristics. Very good agreement between simulations and measured silicon data has been obtained for PMOS and NMOS FinFET transistors. This work demonstrates that the layout sensitivity in discussed design cases can be explained by modulation of the mechanical stress and that the model can be used to predict successfully the stress distributions and their impact on electrical characteristics of FinFET devices. It can be applied to assist designers and technologists with Design-Technology Co-optimization, design rule and PDK development, and process optimization for best performance and reduced variability.
Tomasz BrozekStephen LamChristopher HessLarg Weiland...
126-133页
查看更多>>摘要：Detection and monitoring of the yield loss mechanisms and defects in product chips have been a subject of extensive efforts, resulting in multiple useful Design-for-Manufacturing (DFM) and Design-for-Test (DFT) techniques. Defect inspection techniques extend optical inspection further into sub-10 nm nodes, but many buried defects are formed as a result of multi-layer 3-D interaction, and they are difficult to detect by surface optical scans. In case of a functional failure related to a defect (an open or a short), the localization of the fail site for failure analysis and root cause identification is often difficult, especially for random logic design. In this paper we describe a new -DFM methodology which inserts into the product design special test structures to support New Product Introduction (NPI) and a product yield ramp. The structures are part of PDF Solutions’ proprietary Design-for-Inspection (DFI) system with no penalty to the product layout. They are designed to be electrically tested in a non-contact way using a dedicated and specially optimized e-Beam tool. The layouts of these structures are based on the standard cell design therefore they can be used as filler cells in standard cell-based logic designs. The paper presents the concept of the test structures and their design to cover specific failure modes and enable fail mechanism identification. We describe the design flow to integrate the structures into the product floorplan and the non-contact test methodology to scan product wafers and detect failures. Finally, we demonstrate usage of such DFI structures and provide results collected from scanning product wafers containing embedded DFI filler cells.
查看更多>>摘要：The formation of cone defects is a side effect of the shallow trench isolation (STI) etching process, caused by the redeposition of residue from silicon nitride, silicon dioxide, or byproducts from the etching process. This study aims to explain the mechanism responsible for these defects during STI etching. The utilization of this model can enhance the design for manufacturability by streamlining the manufacturing process, reducing susceptibility to defects and process variations, and ultimately improving the reliability and manufacturability of production.
查看更多>>摘要：This paper describes the art of engineering work that analyzes the causes of yield degradation and contributes yield enhancement through an integrated Engineering for Yield (EFY) framework in the High-Volume Manufacturing (HVM) stage. In this phase, large volumes of wafers are monitored, and defect signatures are clustered to find systematic defects. The yield loss factors are identified through volume diagnosis and the correlation between the sorting yield and the on-chip monitoring sensor is checked. Not only anchoring the production phase analysis but stochastic vulnerabilities which are not expected in the design signoff stage could be discovered through electrical profiling (eProfiling) with Monte-Carlo simulation. This EFY framework improves HVM yield and is applied to the current HVM product portfolio and will continue to be applied to upcoming HVM products. This borderless EFY framework achieves the tangible result of improving the mature yield by >1% by resolving problems that occurred in the HVM stage within a few weeks but also contributes to preventing possible defects for the next HVM products.
查看更多>>摘要：Silicon data allow designers to enhance the chip performance by leveraging machine learning techniques. By gaining a deeper understanding of the distributions of interested features within a wafer, designers can predict chip behaviors more accurately. However, real silicon data may not always be available. This work presents a methodology for generating high-quality synthetic silicon data and verifies its effectiveness through several metrics. Silicon features obtained by chip probing (CP) and wafer acceptance test (WAT) are combined to create more comprehensive data, enabling to conduct design-technology co-optimization (DTCO). Unlike the generative adversarial network (GAN) based methodology used in prior work, this work utilizes a diffusion model to generate synthetic silicon data. The Jensen-Shannon (JS) divergence similarity and Frechet Inception Distance (FID) are used to evaluate the distribution and to quantify the quality of synthetic data, respectively. Experimental results demonstrate that the diffusion model is able to extract the multi-feature silicon data distribution more accurately, with an average JS divergence similarity of 0.987 and an FID of 6.28. This methodology enables to generate a substantial volume of silicon samples for extensive silicon data analysis and DTCO acceleration.
查看更多>>摘要：This study addresses the significant decline in the accuracy of wafer inspection models when the imaging system changes post-training. We propose a domain adaptation method based on semantic segmentation models that maintains accuracy without the need for re-labeling data despite changes in the imaging system. This method was tested on wafers from an actual production line under two different detection environments: a custom-built simple optical system (source domain) and a precision measurement platform (target domain). To align the source and target domain datasets, we introduced an image preprocessing method that adjusts the contrast and brightness of the source domain data based on the histogram distribution of the target domain. We utilized adversarial learning to transfer features from the source to the target domain and modified the segmentation network architecture to prevent overfitting to the source domain data. Additionally, we extended the domain adaptation framework to handle multiple target domains using a multi-discriminator network strategy, enhancing the model’s adaptability to diverse production line environments. Our results demonstrate that compared to the original network, our model significantly improves accuracy with increases of 4.3%, 16.3%, and 11.4% for three different depths of the semantic segmentation model. Furthermore, our proposed network outperforms widely used style transfer methods with performance improvements of 13.2% and 17.3%. Post-processing the output segmentation maps yielded accuracy, precision, and recall scores of 96.8%, 93.5%, and 100%, respectively.
NETL
NSTL
IEEE