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Microprocessors and microsystems
IPC Business Press Limited
Microprocessors and microsystems

IPC Business Press Limited

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0141-9331

Microprocessors and microsystems/Journal Microprocessors and microsystemsSCIEI
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    Hardware security against IP piracy using secure fingerprint encrypted fused amino-acid biometric with facial anthropometric signature

    Sengupta A.Anshul A.Singh A.K.
    1.1-1.14页
    查看更多>>摘要：© 2024 Elsevier B。V。In the era of modern global design supply chain， the emergence of hardware threats is on the rise。 Conventional hardware security techniques may fall short in terms of offering inferior tamper tolerance， unpersuasive digital ownership proof and weaker entropy， for sturdy intellectual property (IP) piracy detection and seamless IP ownership conflict resolution process。 This paper presents a novel hardware security methodology based on IP seller's amino acid biometric and facial anthropometric features to generate an encrypted fused signature using multi-key driven non-invertible fingerprint， for providing sturdy detective countermeasure against IP piracy。 The proposed approach exploits AES framework， where the generated key-translated fingerprint minutiae points of the IP seller is used as an encryption key。 The proposed methodology is highly robust against hardware threats as it capable to generate large size covert security constraints for embedding， as digital evidence， in the IP design during high level synthesis (HLS)。 The results of the proposed approach on comparison with existing approaches， indicates enhanced tamper tolerance ability (against brute force attack) of upto 1。15E+77， lower probability of coincidence or false positive (against ghost signature search attack) of upto 6。72E-06， and stronger entropy of upto 2。06E-138， respectively。
      原文链接:
    • NETL
    • NSTL
    • Elsevier

    Design and implementation of a synchronous Hardware Performance Monitor for a RISC-V space-oriented processor

    Jimenez Arribas M.Martinez Hellin A.Prieto Mateo M.Gamino del Rio I....
    1.1-1.17页
    查看更多>>摘要：© 2024 The AuthorsThe ability to collect statistics about the execution of a program within a CPU is of the utmost importance across all fields of computing since it allows characterizing the timing performance of a program。 This capability is even more relevant in safety-critical software systems， where it is mandatory to analyze the software timing requirements to ensure the correct operation of the programs。 Moreover， in order to properly evaluate and verify the extra-functional properties of these systems， besides timing performance， there are many other statistics available on a CPU， such as those associated with its resource utilization。 In this paper， we showcase a Performance Measurement Unit (PMU)， also known as a Hardware Performance Monitor (HPM)， integrated into a RISC-V On-Board Computer (OBC) designed for space applications by our research group。 The monitoring technique features a novel approach whereby the events triggered are not counted immediately but instead are propagated through the pipeline so that their annotation is synchronized with the executed instruction。 Additionally， we also demonstrate the use of this PMU in a process to characterize the execution model of the processor。 Finally， as an example of the statistics provided by the PMU， the results obtained running the CoreMark and Dhrystone benchmarks on the RISC-V OBC are shown。
      原文链接:
    • NETL
    • NSTL
    • Elsevier

    Hardware-assisted virtualization extensions for LEON processors in mixed-criticality systems

    Losa B.Parra P.Da Silva A.Polo O.R....
    1.1-1.17页
    查看更多>>摘要：© 2024 The AuthorsThe increasing complexity of real-time embedded critical systems has driven the adoption of new methodologies to mitigate high development costs。 One of the most common approaches is the implementation of mixed-criticality systems， characterized by integrating applications with different levels of criticality on the same processing unit。 In these systems， applications run on a separation kernel hypervisor， a software element that controls the execution of the different operating systems， providing a virtualized environment and ensuring the necessary spatial and temporal isolation。 This paper presents the design and implementation of hardware virtualization extensions for LEON processors， whose use is widespread in the field of space systems。 These extensions enable the execution of virtualized applications with minimal transitions to the hypervisor， enhancing system performance。 Our proposed solution defines a specific execution mode and duplicates control and status registers for the exclusive use of virtualized applications。 In addition， the functionality of the hardware and software interrupt signals has been extended， allowing developers to select which ones are handled by the hypervisor and which ones by the guest operating systems directly。 We have implemented the proposed extension using the LEON version 3 processor's original VHDL code， and validated it using exhaustive tests to evaluate performance and resource consumption。 The results show that the proposed modifications allow virtualized applications to execute without hypervisor intervention， matching the performance when non-virtualized while significantly outperforming existing para-virtualization solutions。 Resource consumption increases by 6% to 14%， depending on the FPGA， which is low when compared to available resources。 Power consumption increases by only a few milliwatts， which can be considered negligible。
      原文链接:
    • NETL
    • NSTL
    • Elsevier