Structure Design and Characteristics Research of 1 000 V 4H-SiC VDMOS
This study focuses on designing and optimizing a 1 000 V vertical double-diffusion metal oxide semiconductor(VDMOS)field-effect transistor using 4H-SiC.Leveraging Silvaco simulation software,we comprehensively investigate the relationship between device parameters and withstand voltage characteristics,aiming for a 50％margin.Following optimization,the device achieves a threshold voltage of 2.3 V,with the breakdown voltage reaching 1 525 V.Compared with an Si-based VDMOS under identical withstand voltage conditions,the breakdown voltage of the 4H-SiC VDMOS increases by 12％.Notably,the surface electric field distribution of the 4H-SiC VDMOS during breakdown remains relatively uniform,with a maximum value of 3.4X 106 V/cm.The effective terminal length measures at 15 μm,approximately 6％that of an Si-based VDMOS,with the overall area reducing by nearly 1/10.Furthermore,the structure is simpler compared to that of the 4H-SiC VDMOS under identical withstand voltage conditions.It involves no additional process steps,thus facilitating easy device fabrication.
4H-SiCVDMOSbreakdown voltagedrift zone parameterschannel length
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