An On-Chip High Precision Adaptive Ramp Generator with Anti-PVT-Variation for CIS Column-Level ADC
The traditional on-chip global ramp generator circuit is significantly affected by process,voltage,and temperature (PVT),resulting in ramp signal distortion and poor linearity. Moreover,calibration becomes difficult owing to parasitic effects. Therefore,in this study,we introduced an adaptive ramp generator that resists PVT variations. We fine-tuned the ramp using a successive approximation algorithm and a fixed-step search method and achieved a two-point slope correction. The ramp calibration circuit included a resistive DAC (RDAC),current-mode DAC (IDAC),logic control,dynamic comparator,and other modules. The average calibration period for the adaptive ramp generator was found to be approximately 1.143ms. Post calibration,DNL of the adaptive ramp generator was+0.00207/-0.00115LSB and INL was+0.6755/-0.3887LSB. Under various PVT conditions,the calibration voltage error was less than 1.5LSB and power consumption was as low as 1.155mW. Compared with traditional ramp generators,the proposed adaptive generator is advantageous in terms of higher precision and lower power consumption.
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维普
