Design of A Configurable Segmented FFE High-Speed SerDes Transmitter
In this study,we implemented a 56Gb/s NRZ and 112Gb/s PAM-4 dual-mode transmitter design on a 28nm CMOS process. For the equalization,we used a data multiplexing architecture to support a fully configurable segmented feed-forward equalizer (FFE). Next,we adopted a current-mode logic (CML) driver topology,with a pull-up current source,as the terminal output network. The key circuit structures and techniques included relying on a paragraph allocation module to allocate paragraphs for the FFE and achieving coarse adjustments of the tap weights. We utilized a pre-charged 1-UI pulse generator and 4∶1 MUX to enhance the bandwidth. The driver incorporated a load-side parallel current source to boost the common-mode voltage and a T-coil to extend the output bandwidth and swing. Our simulation results demonstrated that the eye heights for the 112Gb/s PAM4 and 56Gb/s NRZ output were 40 and 130mV,respectively.
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