Design of Acceleration Unit of Encoding and Frame Generation for PAICORE2.0
An edge computing system was designed by the spiking neural network chip PAICORE2.0 of Peking University,in conjunction with Xilinx ZYNQ. However,the software encoding and frame generation processes on the processing system (PS) side is slow and limits the performance of the system. Therefore,a hardware acceleration method is proposed. The software encoding and frame generation processes,which is serially executed on the PS side,is moved to the data path on the programmable logic (PL) side for pipelined parallel execution. The hardware acceleration unit mainly consists of highly parallel convolution units,parameterizable spiking neurons,width-balanced data buffers and other modules. The results show that the method removes the time overhead of software encoding and frame generation without increasing the data path transmission delay. In the example of CIFAR-10 image classification,compared with software encoding and frame generation,the hardware encoding and frame generation module results in only a marginal increase in resource utilization—9.3％ more Look-Up Tables (LUTs),3.7％ more Block RAMs (BRAMs),2.6％ more flip-flops (FFs),0.9％ more LUTRAMs,and 14.9％ more digital signal processors (DSPs),as well as a 14.6％ increase in power consumption. However,it achieves approximately an 8.72-fold improvement in inference speed.
spike neural network chipPAICORE2.0ZYNQspike encodinghardware accelerationconvolutional acceleration unit
万方数据
维普
