Implementation of an Improved LeNet Traffic Sign Multi-classification Heterogeneous Accelerator
An implementation of traffic sign multi-classification heterogeneous accelerator based on improved LeNet is proposed.The accelerator utilizes an ARM+FPGA heterogeneous platform to deploy the forward inference of the improved LeNet on the FPGA for parallel computing.On the FPGA side,the AXI-Stream protocol is employed with DMA to achieve high-speed data streaming,and techniques such as array partitioning and multi-level pipeline are utilized for parallel data processing.On the ARM side,the PYNQ framework is used for data updates and accelerator scheduling.Experimental results on GTSRB demonstrate that proposed design achieves an average inference time of 14.489 ms at a working clock frequency of 50 MHz,compared to 710 ms on the MCU,resulting in a speedup of up to 49 times.This design provides significant assistance for edge applications involving traffic sign multi-classification.
万方数据
维普
