A 3.125 Gb/s adaptive analog equalizer is designed in a standard 0.18 μm CMOS process. A novel active nega-tive feedback structure is adopted to improve the bandwidth and gain compensation range of the equalization filter. The adaptive control loop employs a single-loop structure including a slicer,which adjusts the high-frequency gain by detecting the slope of the signal to generate different adjustment voltages,so that the channels of different lengths can be adaptively compensated. It can be seen from the results that the jitter of output signals are 0.24 UI and 0.31 UI at 3.125 Gb/s and 4 Gb/s. The channel losses that can be compensated 13.04～22.04 dB and 16.94～28.50 dB at 1.5625 GHz and 2 GHz,and the output swing of the equalized signals are 270 mV. Under 1.8 V supply voltage,the total power consumption is 59.4 mW.
analog equalizeradaptive control loopactive negative feedbackslope-detection
万方数据
维普
