为了延长宽输入电子设备的续航时间,设计了一种低静态电流低压差线性稳压器(low dropout regulator,LDO).设计中将带隙基准电路所有的MOS管设置在亚阈值区,同时添加一条快速上电通路,这样在兼顾上电时间的同时又保证了低静态电流的需求.利用动态电流偏置技术和瞬态增强电路,解决低静态电流和瞬态响应的矛盾;采用伪等效串联电阻(equiralent series resistance,ESR)补偿、零点补偿等方法,解决低静态电流和稳定性的矛盾.芯片采用0.18 μm 30 V BCD工艺.LDO输入电压为2.7～30 V,输出电压为1.2～6.5 V,最大负载电流150 mA.仿真结果表明,该LDO的静态电流仅1.3 μA,负载电流在1～150 mA跳变时,上冲电压为54 mV,下冲电压为75 mV.
Design of a low quiescent current LDO
To extend the battery life of wide-input electronic devices,this paper presents a low static current low dropout regulator(LDO).In the design,all MOS transistors in the bandgap reference circuit are operated in the subthreshold re-gion,and a fast power-on path is added to balance the power-on time while ensuring low static current requirements.Dy-namic current biasing techniques and transient enhancement circuits are employed to resolve the contradiction between low static current and transient response.Additionally,methods such as pseudo-equivalent series resistance(ESR)compensa-tion and zero compensation are utilized to address the conflict between low static current and stability.The chip is fabricated using a 0.18 μm 30 V BCD process.The LDO operates with an input voltage range of 2.7 to 30 V,an output voltage range of 1.2 to 6.5 V,and a maximum load current of 150 mA.Simulation results show that the LDO achieves a static current of only 1.3 μA,with a voltage overshoot of 54 mV and a voltage undershoot of 75 mV when the load current switches between 1 mA and 150 mA.
low dropout linear regulatorlow quiescent currentdynamic current bias technologytransient response
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维普
