首页|一种带有错误抑制机制的低复杂度Turbo乘积码译码器

一种带有错误抑制机制的低复杂度Turbo乘积码译码器

扫码查看
针对Turbo乘积码(Turbo Product Code,TPC)迭代译码过程中的错误传播问题,设计了一种极低复杂度的错误抑制机制,对错误定位精准且简单高效,可有效降低迭代初期的不可靠外信息对误码率(Bit Error Rate,BER)性能的负面影响.所提译码算法的迭代收敛速度较经典的Chase算法优势明显,在第3 次迭代时,其误码率曲线基本和Chase算法4 次迭代的性能持平,在同等性能下可降低25%译码时延.同时,在现场可编程门阵列(Field Programmable Gate Array,FPGA)中设计了一种软输入软输出(Soft-Input Soft-Output,SISO)译码器,通过将测试序列生成模块与校验子计算模块、欧氏距离计算模块并行化设计获得了较低的译码时延,利用递归运算极大降低了算术复杂度,在与Xilinx官方的TPC译码IP核吞吐量相当的情况下消耗更少的硬件资源.
A Low-complexity Turbo Product Code Decoder with Error Suppression Mechanism
For the problem of error propagation in the iterative decoding process of Turbo product code(TPC),a very low-complexity error suppression mechanism is designed,which is accurate,simple and efficient in error localization,and can effectively reduce the negative impact of unreliable external information at the beginning of the iteration on the bit error rate(BER)performance.The iterative convergence speed of the proposed decoding algorithm has obvious advantages over the classical Chase algorithm,and in the third iteration,its BER curve can be almost equal to that of the Chase algorithm in four iterations,and the decoding delay can be reduced by 25%under the same performance.At the same time,a soft-input soft-output(SISO)decoder is designed in the field programmable gate array(FPGA),which obtains low decoding latency by parallelizing the test sequence generation module with the syndrome computation module and the Euclidean distance computation module,greatly reduces the arithmetic complexity by using recursive operations,and consumes fewer hardware resources with the same throughput as that of Xilinx's official TPC decoding IP core.

Turbo product codesoft decision decodinglow complexitylow latency

巩克现、闫瑾、刘宏华、王玮

展开 >

郑州大学 电气与信息工程学院,郑州 450001

中国电子科技集团公司第二十七研究所,郑州 450047

Turbo乘积码 软判决译码 低复杂度 低时延

2025

电讯技术
中国西南电子技术研究所

电讯技术

北大核心
影响因子:0.472
ISSN:1001-893X
年,卷(期):2025.65(1)