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基于IEEE802.1AS的多跳时钟同步算法与系统实现

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  • 国家科技期刊平台
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针对现有IEEE 802.1AS协议中单一主时钟无法保障多跳网络下高精度同步的问题,提出一种基于多属性决策的冗余时钟同步方法.首先,基于链路拥塞程度、节点拓扑属性和时钟源质量系数对时钟属性值进行建模;其次,采用多属性决策算法选取最佳主时钟并生成冗余时钟序列表;最后,利用FPGA(Field Programmable Gate Array)平台设计并实现冗余时钟同步系统,同时搭建真实网络环境对所提方法进行测试.结果表明,相较于现有方法,时钟同步精度提升了68%,主时钟失效后重新同步所需收敛时间减小了60%.
Multi-Hop Clock Synchronization Algorithm and System Implementation Based on IEEE 802.1AS
Aiming at the problem that a single master clock in the existing IEEE 802.1AS protocol cannot guarantee the high precision of clock synchronization in multi-hop network,a redundant clock synchronization method based on multi-attribute decision-making is proposed.Firstly,the clock attribute value is modeled based on the link congestion degree,to-pology attribute of node and clock source quality factor.Secondly,the multi-attribute decision-making algorithm is used to select the best master clock and generate a redundant clock sequence table;Finally,the redundant clock synchronization sys-tem is designed and implemented on field programmable gate array(FPGA)platform,and a real network environment is constructed to test the proposed method.The results show that,compared with the existing methods,the clock synchroniza-tion accuracy is improved by 68%,and the convergence time required for resynchronization after master clock failure is re-duced by 60%.

clock synchronizationIEEE 802.1AS protocolmaster clock selectionredundant clockFPGA

赵国锋、危瑞鹏、邢媛、徐川、张汝凤

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重庆邮电大学通信与信息工程学院,重庆 400065

时钟同步 IEEE 802.1AS协议 主时钟选取 冗余时钟 FPGA

国家自然科学基金国家重点研发计划国家重点研发计划重庆市研究生科研创新项目重庆邮电大学博士研究生人才培养项目

621710702018YFB18003012018YFB1800304CYB19176BYJS201905

2024

10.12263/DZXB.20220304

电子学报
中国电子学会

电子学报

CSTPCD北大核心
影响因子：1.237
ISSN：0372-2112
年,卷(期)：2024.52(3)
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