基于IEEE802.1AS的多跳时钟同步算法与系统实现
Multi-Hop Clock Synchronization Algorithm and System Implementation Based on IEEE 802.1AS
赵国锋 1危瑞鹏 1邢媛 1徐川 1张汝凤1
作者信息
- 1. 重庆邮电大学通信与信息工程学院,重庆 400065
- 折叠
摘要
针对现有IEEE 802.1AS协议中单一主时钟无法保障多跳网络下高精度同步的问题,提出一种基于多属性决策的冗余时钟同步方法.首先,基于链路拥塞程度、节点拓扑属性和时钟源质量系数对时钟属性值进行建模;其次,采用多属性决策算法选取最佳主时钟并生成冗余时钟序列表;最后,利用FPGA(Field Programmable Gate Array)平台设计并实现冗余时钟同步系统,同时搭建真实网络环境对所提方法进行测试.结果表明,相较于现有方法,时钟同步精度提升了68%,主时钟失效后重新同步所需收敛时间减小了60%.
Abstract
Aiming at the problem that a single master clock in the existing IEEE 802.1AS protocol cannot guarantee the high precision of clock synchronization in multi-hop network,a redundant clock synchronization method based on multi-attribute decision-making is proposed.Firstly,the clock attribute value is modeled based on the link congestion degree,to-pology attribute of node and clock source quality factor.Secondly,the multi-attribute decision-making algorithm is used to select the best master clock and generate a redundant clock sequence table;Finally,the redundant clock synchronization sys-tem is designed and implemented on field programmable gate array(FPGA)platform,and a real network environment is constructed to test the proposed method.The results show that,compared with the existing methods,the clock synchroniza-tion accuracy is improved by 68%,and the convergence time required for resynchronization after master clock failure is re-duced by 60%.
关键词
时钟同步/IEEE/802.1AS协议/主时钟选取/冗余时钟/FPGAKey words
clock synchronization/IEEE 802.1AS protocol/master clock selection/redundant clock/FPGA引用本文复制引用
基金项目
国家自然科学基金(62171070)
国家重点研发计划(2018YFB1800301)
国家重点研发计划(2018YFB1800304)
重庆市研究生科研创新项目(CYB19176)
重庆邮电大学博士研究生人才培养项目(BYJS201905)
出版年
2024
国家科技期刊平台
NSTL
万方数据