Aiming at the increasing demand for low-area and high-throughput encryption algorithms in IoT chips,three SM4 lightweight optimization hardware implementation schemes are proposed,which are speed priority,area priority,and area-speed trade-off. In the area priority scheme,the linear function L/L' is optimized to reduce the use of 48-bit regis-ters and 120-bit XOR resources. In the speed priority scheme,two new S-boxes are introduced to realize the combination of the linear function L/L' and the look-up table S-box,so as to avoid the delay of the linear function L/L'. In the area-speed trade-off scheme,the S-box linear mapping,the inverse linear mapping and the linear function L/L' are merged into a func-tion,and the encryption calculation is mapped to the composite filed,the delay of the S-box linear mapping can be reduced and the speed can be further improved. Compared with the existing schemes,the area of the area priority scheme is reduced by 5.5％～44.8％ (only 2371 GE),the power consumption is only 0.88 mW,and the maximum frequency is 324 MHz;the ar-ea of the speed priority scheme is 3061 GE,and the maximum frequency is increased by more than 9.8％,up to 549 MHz,with a throughput rate of 439.2 Mbps.
关键词
物联网/SM4/轻量级/S盒/优化设计
Key words
Internet of things/SM4/lightweight/S-box/optimization design
维普
万方数据