针对物联网传感器难以同时满足高分辨率与低功耗的瓶颈问题,本文设计了一种伪三阶离散时间del-ta-sigma调制器.该架构将一阶无源噪声整形SAR(Successive Approximation Register)量化器嵌入传统二阶delta-sigma调制器以实现更强的噪声整形能力.本文设计允许系统在更低的过采样率(Over Sampling Ratio,OSR)下获取更高的峰值SQNR(Signal-to-Quantizing Noise Ratio),有效缓解了系统精度和功耗之间的设计矛盾,并且减少了有源积分器的使用.针对传统有源加法器高功耗和无源加法器存在衰减不确定性的问题,本文提出了一种新型前馈求和量化电路,它具有对衰减不敏感的优势并且降低了第二级有源积分器的驱动压力,这进一步降低了系统的功耗.本文提出的del-ta-sigma调制器采用180 nm CMOS(Complementary Metal Oxide Semiconductor)工艺制造并测试.在电源电压1.4 V下,芯片测试功耗为47.2μW.在带宽为8 kHz的测试条件下,调制器的DR(Dynamic Range)、峰值SNDR(Signal-to-Noise and Distortion Ratio)和SFDR(Spurious-Free Dynamic Range)分别为97.2dB,96.6dB和114.4dB.因此,Schreier和Walden的SNDR FoM(Figure of Merit)优值达到了178.9dB和0.053 pJ/step.本文提出的伪三阶delta-sigma调制器在功耗和分辨率之间实现了较好的权衡,为物联网领域的低功耗高分辨率调制器设计提供了较好的解决方案.
Pseudo Third-Order Delta-Sigma Modulator Applied to Internet of Things Sensors
This paper proposes a pseudo third-order discrete-time delta-sigma modulator to address the bottleneck of high resolution and low power consumption in Internet of Things (IoT) sensors. This architecture embeds a first-order pas-sive noise-shaping SAR (Successive Approximation Register) quantizer into a conventional second-order delta-sigma modu-lator to achieve stronger noise-shaping capabilities. This allows the system to achieve higher peak SQNR (Signal-to-Quan-tizing Noise Ratio) at lower OSR (Over Sampling Ratio),effectively mitigating the design trade-off between system accura-cy and power consumption,while reducing the use of active integrators. In response to the high power consumption of tradi-tional active adders and the attenuation uncertainty of passive adders,this paper proposes a novel feedforward sum quantiza-tion circuit. It has the advantage of being insensitive to attenuation and reduces the driving pressure of the second stage ac-tive integrator,which further reduces the power consumption of the system. The proposed delta-sigma modulator is manu-factured and tested using a 180 nm CMOS (Complementary Metal Oxide Semiconductor) process. At a power supply volt-age of 1.4 V,the tested power consumption of the chip is 47.2 μW. With a bandwidth of 8 kHz,the DR (Dynamic Range),peak SNDR (Signal-to-Noise and Distortion Ratio),and SFDR (Spurious-Free Dynamic Range) of the modulator are 97.2dB,96.6dB,and 114.4dB,respectively. Therefore,figure-of-merit (FoM) Schreier and Walden for SNDR are 178.9dB and 0.053 pJ/step. The pseudo third-order delta-sigma modulator proposed in this article achieves a good balance between power consumption and resolution,providing a good solution for low-power and high-resolution modulator design in the field of the IoTs.
internet of thingsdelta-sigma modulatorlow powerhigh resolution
万方数据
维普
