首页|1500 V超结功率MOS器件优化与电容特性研究

1500 V超结功率MOS器件优化与电容特性研究

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本文利用半超结结构进行高压超结功率金属氧化物半导体(Metal Oxide Semiconductor,MOS)器件的设计,基于Sentaurus TCAD(Technology Computer Aided Design)仿真平台设计超结元胞结构并优化高压超结功率MOS器件的击穿电压与导通电阻,随后探究了寄生电容的特性.最后,基于多次外延工艺自主设计出一款器件结构仿真击穿电压1658 V、工艺仿真击穿电压1598 V、比导通电阻值303 mΩ·cm2的高压超结功率MOS器件,与相同耐压值器件相比,比导通电阻值下降约50%.同时探究了超结掺杂浓度与厚度以及电压支持层掺杂浓度与厚度4个主要结构参数对器件寄生电容特性的影响.
Optimization and Capacitance Characteristics of 1500 V Super Junction Power MOS Devices
In this paper,the design of high-voltage super junction power MOS (Metal Oxide Semiconductor) de-vice is carried out by using the semi-super junction structure,the super junction cell structure is designed based on the Sentaurus TCAD (Technology Computer Aided Design) simulation platform,and the breakdown voltage and on-resis-tance of the high-voltage super junction power MOS devices are optimized,and then the characteristics of parasitic ca-pacitance are explored. Finally,based on multiple epitaxial processes,a high-voltage super junction power MOS device with a simulated breakdown voltage of 1658 V,a process simulation breakdown voltage of 1598 V and a specific on-resistance value of 303 mΩ·cm2 has been independently designed,which reduced the specific on-resistance value by about 50% compared with the same withstand voltage device. At the same time,the influence of four main structural pa-rameters,namely super junction doping concentration and thickness and voltage support layer doping concentration and thickness,on the parasitic capacitance characteristics of the device has been explored.

super junction VDMOScellbreakdown voltagespecific on-resistanceparasitic capacitance

种一宁、李珏、乔明

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电子科技大学电子薄膜与集成器件全国重点实验室,四川成都 611731

电子科技大学广东电子信息工程研究院,广东东莞 523950

电子科技大学(深圳)高等研究院,广东深圳 518110

超结VDMOS 元胞 击穿电压 比导通电阻 寄生电容

广东省基础与应用基础研究基金国家自然科学基金航空科学基金

2021B151502003162174024201943080002

2024

电子学报
中国电子学会

电子学报

CSTPCD北大核心
影响因子:1.237
ISSN:0372-2112
年,卷(期):2024.52(7)