本文提出了一种新型高带宽密度、低功耗的面向片上(Die to Die,D2D)互连的7阶相关非归零(Non-Re-turn-to-Zero,NRZ)编码接口电路结构.为了进一步提高5阶相关NRZ编码在D2D互连中的信噪比和带宽密度,设计了基于发射矩阵和接收矩阵的编解码电路.基于发射矩阵,在发射端设计了基于电压模驱动的编码电路,有效降低了功耗;基于接收矩阵,在接收端设计了基于有源可调电感的解码均衡电路,提高了通信速率.同时,为了解决接收端时钟偏斜问题,还设计了误码校准电路.该接口电路采用28 nm CMOS(Complementary Metal Oxide Semiconductor)工艺设计,核心面积为3 mm2,可适用于10～50 mm的片上互连.后端仿真结果表明,在奈奎斯特频率为20 GHz、信道插损为-8 dB的条件下,接收端最窄眼宽为0.45 UI,误码率小于10-15,能耗效率为1.2 pJ/b,带宽密度为448 Gbps/mm.
Design of D2D Interface Based on 7-Order Correlated NRZ Coding
In this paper,a novel high-bandwidth density and low-power 7-order correlated NRZ(Non-Return-to-Ze-ro)coding interface circuit for D2D(Die to Die)interconnection is proposed.In order to further improve the SNR(signal-to-noise ratio)and bandwidth density of 5-order correlated NRZ coding,this paper designs encoding and decoding circuits based on transmission and reception matrices.Based on the transmission matrix,a voltage-mode encoding circuit is de-signed at the transmitting end to effectively reduce power consumption.Based on the reception matrix,a decoding equaliza-tion circuit based on active adjustable inductor is designed at the receiving end to improve communication speed.In order to solve the problem of clock skew at the receiving end,this paper also designs an error correction circuit.The interface cir-cuit is designed using 28 nm CMOS(Complementary Metal Oxide Semiconductor)technology,with a core area of 3 mm2,and can be applied to on-chip interconnects ranging from 10 to 50 mm.The backend simulation results indicate that,under the condition of a Nyquist frequency of 20 GHz and a channel loss of-8 dB,the receiver's narrowest eye width is 0.45 UI,with a bit error rate less than 10-15,energy efficiency of 1.2 pJ/b,and bandwidth density of 448 Gbps/mm.
die to diecorrelated non-return-to-zero codingbandwidth densitywireline transceiversource-series terminatedactive inductor
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维普
