低延迟分组密码的设计是目前密码学研究中的热点之一,其中低延迟S盒的构造是设计中的重要研究方向.本文基于低延迟门电路和两层树型结构,搜索不同延迟水平下具有一定密码学性质的低延迟平衡布尔函数及其拓展比特置换等价类;基于将低延迟布尔函数作为分量布尔函数构造向量布尔函数的方法,本文构造得到了不同延迟水平下的低延迟S盒,并给出延迟性质和硬件实现面积具有优势的S盒实例;此外,本文对低延迟的S盒集合与逆S盒集合匹配搜索具有双向低延迟性质的S盒,给出搜索得到的实例.与PRINCE、MANTIS等其他低延迟分组密码中使用的4 bit S盒相比,本文构造的低延迟S盒在延迟水平上相较MANTIS降低了20%,与PRINCE相比降低了33%,在硬件实现面积上相较MANTIS减少了6.68%,与PRINCE相比减少了17.69%.
Research on Construction of Low-Latency S-Boxes and Bidirectional Low-Latency Properties
The quest for low-latency block ciphers is a burgeoning area of interest within the cryptographic community,with the development of low-latency S-boxes standing as a pivotal avenue of exploration.Leveraging gate circuits of minimal latency and a novel two-layer tree structure,our study delves into the construction of balanced Boolean functions and their ex-tended bit permutation equivalence classes that manifest desirable cryptographic properties across varied latency thresholds.Utilizing these low-latency Boolean functions as coordinate functions,we craft vectorial Boolean functions to construct S-boxes with low-latency.Our research not only furnishes S-boxes optimized for latency performance and hardware implementa-tion area but also pioneers the amalgamation of low-latency S-box sets with their corresponding inverse sets,searching for S-boxes with bidirectional low-latency property.The low-latency S-box in our investigation outperform existing benchmarks and offer more choices,showcasing a latency reduction of 20%and 33%over MANTIS and PRINCE,alongside achieving a hardware area reduction of 6.68%compared to MANTIS and a substantial improvement of 17.69%against PRINCE.
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