一种抑制ESD保护电路闩锁效应的版图研究
Study on the layout with characteristic of preventing latch-up in ESD protection circuit
柴常春 1张冰 1杨银堂 1吴晓鹏 1王婧1
作者信息
- 1. 西安电子科技大学宽禁带半导体材料与器件教育部重点实验室,陕西西安710071
- 折叠
摘要
针对具有低压触发特性的静电放电(electrostatic discharge,ESD)保护电路易闩锁的不足,本文结合CSMC 0.6μm CMOS工艺,设计了一种可应用于ESD保护电路中的独立双阱隔离布局方案,这种方案不仅可以有效的阻断形成闩锁的CMOS器件固有纵向PNP与横向NPN晶体管的耦合,且兼容原有工艺而不增加版图面积.将此布局方案与常规保护环结构同时应用于笔者研制的具有低压快速触发特性双通路ESD保护电路中,通过流片及测试对比表明,该布局方案在不影响保护电路特性的同时,较常规保护环结构更为有效的克服了保护电路的闩锁效应,从而进一步提升了该保护电路的鲁棒性指标.本文的布局方案为次亚微米MOS ESD保护电路版图设计提供了一种新的参考依据.
Abstract
Considering the defiiency that electrostatic discharge (ESD) protection circuit which has characteristic of low trigger voltage is easy to lead to latch-up,and combining with the CSMC 0.6μtm CMOS process,a layout scheme of independent double-well isolation that can be applied in the ESD protection circuit is presented in this paper.This scheme can not only effectively block the coupling of the latched up CMOS device's inherent vertical PNP and lateral NPN transistor,but also be compatible with the original process without increasing the layout area.The scheme and the conventional guard ring structure are both applied torthe dual-channel ESD protection circuit with characteristic of low-voltage triggering,which is developed by the author.Fabricating and testing by comparison show that comparing with the conventional guard ring structure,in the meanwhile not affecting the characteristic of the protection circuit,this layout scheme is more effective in preventing the latch-up,which thereby further enhancing the circuit's robustness.This layout scheme offers a new reference for the layout design of the sub-submicron MOS ESD protection circuit.
关键词
闩锁效应/静电放电/版图/独立双阱隔离Key words
latch-up effect/electrostatic discharge/layout/independent double-well isolation引用本文复制引用
基金项目
国家自然科学基金(60776034)
中央高校基本科研业务费专项资金资助(K50510250002)
出版年
2013
NETL
NSTL
维普
万方数据