65纳米工艺下低功耗高线性度音频∑△模数转换器的研究与实现
Research and implementation of a low-power high-linearity audio ΣΔ ADC in 65nm process
曹天霖 1孙颖 1韩雁 1梁国 1廖璐 1罗豪1
作者信息
- 1. 浙江大学信电系微电子与光电子研究所,浙江杭州310027
- 折叠
摘要
本论文设计了一款适合音频应用的低功耗、高线性度ΣΔ ADC.此ADC包含了高性能2-1级联单比特量化∑△调制器和采用ROM、RAM设计的低功耗,高面积利用率数字抽取滤波器.此款ADC芯片采用中芯国际65nm 1P8M混合信号CMOS制作工艺,核心面积为0.581平方毫米.测试结果表明,本文设计的ΣΔ ADC在22.05kHz的音频带宽内,采样频率为5MHz时最高信噪失真比可达90dB,动态范围为93dB,在1.2V供电电压下功耗为2.2mW,同时实现了高性能与低功耗.
Abstract
We designed an audio ΣΔ ADC which has low power consumption and high linearity.The proposed ΣΔ ADC contains a 2-1 cascaded 1-bit ΣΔ modulator and a low-power,area-efficient digital decimation filter which is designed using RAM and ROM.This chip has been implemented in SMIC 65nm mixed-signal 1P8M CMOS standard silicon process,and the die area is 0.581mm2.Experiment results shown that 90dB signal to noise plus distortion ratio (SNDR) and 93dB dynamic range (DR) are achieved within 22.05kHz audio band,at 5M Hz sample rate.The ADC's power dissipation is 2.2mW under 1.2V supply voltage,which means that this chip obtains high-performance and low-power at the same time.
关键词
ΣΔADC/低功耗/高线性度/音频应用Key words
ΣΔ ADC/low-power/high-linearity/audio applications引用本文复制引用
基金项目
国家自然科学基金(61274035)
浙江省创新创业孵化项目()
出版年
2013
NETL
NSTL
万方数据