CABAC二值化建模器的硬件优化设计
Optimized hardware design of CABAC binarizer and context modeler
彭斌 1丁丹丹 1虞露1
作者信息
- 1. 浙江大学信息与电子工程学系,浙江杭州310027
- 折叠
摘要
提出一种二值化建模器的语法元素拆分合并策略及对应的硬件结构,能够使二元位串长度的分布更集中更平坦,从而提高了H.264/AVC中基于上下文的自适应二进制算术编码器(CABAC)的吞吐率和硬件资源利用率.本文使用生产者/消费者模型为CABAC编码器建模进行数据统计和分析,发现通过合并特定语法元素使二元位串平均长度增加可以提高CABAC编码器的吞吐率,而通过分割特定语法元素使二元位串长度的峰值更小变化更均匀可以增加硬件资源的利用率.仿真结果显示该设计平均每节拍能够处理1.89个二元位,该设计在0.13 μm CMOS工艺下综合工作频率可达303MHz,相应资源占用为22.26K门.
Abstract
This paper presents a hardware architecture of binarizer and context modeler which are two parts of the CABAC entropy encoder of H.264/AVC.A producer/consumer model is applied to CABAC encoder showing that the throughput of CABAC encoder is improved and the utilization ratio of hardware resources is raised by optimizing the distribution of the length of bin string produced by binarizer and context modeler.Based on the model analysis,a three-stage pipelined hardware architecture with syntax element (SE) merging and splitting strategies are proposed for the optimization of bin string length distribution.Simulation results show that our design processes 1.89 bins per cycle on average.It can work at 303 MHz with 22.26K gates targeting 0.13 μm CMOS process.
关键词
视频编码/H.264/AVC/CABAC/硬件结构设计Key words
video coding/H.264/AVC/CABAC/hardware design引用本文复制引用
基金项目
国家自然科学基金()
中央高校基本科研业务费专项资金资助()
出版年
2013
NETL
NSTL
维普
万方数据