一种快速计算和优化关键面积提高成品率的方法
A fast method for extracting and optimizing critical area to improve yield
朱椒娇 1罗小华 1陈利升 1叶翼 1严晓浪1
作者信息
- 1. 浙江大学电气学院、超大规模集成电路设计研究所,浙江杭州310027
- 折叠
摘要
成品率驱动设计(DFY)已经成为集成电路设计的必然趋势.基于随机缺陷的DFY设计的主要目标是通过优化版图的关键面积来提高成品率.针对版图局部修改后关键面积的重新计算问题,提出了一种快速计算关键面积的方法,不仅能快速比较各种修改方案的优劣,还能利用计算速度的优势,快速得到最优的设计修改方案,极大的降低了DFY设计的计算时间成本,提高集成电路产品的成品率.
Abstract
Design for yield (DFY) has become inevitable trend in IC design.As for the yield related to random defect,the purpose of DFY is optimizing critical area of a design layout to improve yield.Aiming at the massive re-extraction of critical area after modifications to the layout,this paper proposes a new method to deal with this problem.The new critical area can be fast extracted and the best modification option can be fast determined,which results in a higher yield with less computational time cost of DFY flow.
关键词
成品率驱动设计(DFY)/关键面积/Voronoi图Key words
design for yield/critical area/Voronoi diagram引用本文复制引用
出版年
2013
NETL
NSTL
维普
万方数据