To study the degradation mechanism of silicon carbide metal-oxide-semiconductor field effect transistors (SiC MOSFETs) under dynamic drain-source stress, a dynamic reverse bias test platform with an adjustable dV ds/dt capability up to 80 V/ns was developed. A dynamic high-temperature reverse bias test of commercial SiC MOSFET was carried out, and the effect of dynamic drain-source stress with a high voltage change rate on the electrical characteristics of SiC MOSFET was discussed. Experimental results show that the threshold voltage and forward conduction voltage of the bulk diode increased, indicating that the gate oxygen layer and the bulk diode above the JFET region of the device may be degraded. Sentaurus TCAD was used to analyze the weak position of plane-gate SiC MOSFET under high drain-source voltage and a high voltage change rate, and hole traps were set at the gate oxygen layer junction and the body diode region to simulate the effect of dynamic high-temperature reverse bias on the dynamic and static parameters of SiC MOSFET.
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