电子测试2024,Issue(2) :19-22.

基于统一功耗格式文件的低功耗模块自动化ECO方法研究

Research on automated ECO method of low-power modules based on unified power consumption format files

袁峰 叶煜 魏星 刁屹 杨晓庆 丁琳 李杨
电子测试2024,Issue(2) :19-22.

基于统一功耗格式文件的低功耗模块自动化ECO方法研究

Research on automated ECO method of low-power modules based on unified power consumption format files

袁峰 1叶煜 1魏星 1刁屹 1杨晓庆 1丁琳 1李杨1
扫码查看

作者信息

  • 1. 奇捷科技(深圳)有限公司 深圳 518000
  • 折叠

摘要

现有的对LP模块进行修改或调整的流程一般分为人工调整和重新综合两种,且存在明显不足与局限之处.若使用人工,在集成电路规模较大时会耗费大量时间,得到的结果也极其容易产生错误.若使用修改后的UPF与RTL文件重新综合出门级网表,此举相当于将之前已经走过的设计流程重新走一遍,会耗费大量时间,大幅拉长芯片更新迭代的周期.基于现有流程存在的不足与局限性,提出 4 种对LP模块进行ECO的自动化新流程,通过自动化对功耗模块进行电路设计变更处理,降低出现错误的情况,同时能极大提高芯片设计流程更新迭代的效率和速度.

Abstract

The existing process of modifying or adjusting LP modules is generally divided into two forms:manual adjustment and re-synthesis.There are obvious shortcomings and limitations:if manual labor is used,it will take a lot of time when the integrated circuit is large-scale,and the results obtained are extremely prone to errors.If the modified UPF and RTL files are used to re-integrate the door-level netlist,this is equivalent to going through the design process that has already been gone through before,which will consume a lot of time and greatly lengthen the cycle of chip update and iteration.Based on the shortcomings and limitations of the existing process,this paper proposes four new automated processes for ECO LP modules,which can reduce the occurrence of errors and greatly improve the efficiency and speed of the update and iteration of the chip design process by automating the circuit design change processing of the power consumption module.

关键词

集成电路/门级网表/LP模块/芯片设计/ECO

Key words

IC/door-level netlist/LP modules/chip design/ECO

引用本文复制引用

出版年

2024
电子测试
北京自动测试技术研究所

电子测试

影响因子:0.332
ISSN:1000-8519
浏览量1
段落导航相关论文