This paper describes domestic 0.18 μ m technology to design and implement a low jitter phase-locked loop,and proposes a structure of a third-order low-pass sampling filter to optimize phase noise.The power consumption of the phase-locked loop is 60mW in the locked state,and the phase noise is 97.61 dB/Hz under a frequency offset of 10kHz.
关键词
数字音频/锁相环/低通滤波器/抖动/相位噪声
Key words
digital audio/phase locked loop/low pass filter/jitter/phase noise
维普
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