Design of High Area Efficiency Elliptic Curve Scalar Multiplier Based on Fast Modulo Reduction of Bit Reorganization
To solve the problem that existing elliptic curve cryptography scalar multipliers are difficult to balance flexibility and area efficiency,a scalar multiplier with high area efficiency based on bit reorganization fast modular reduction is designed.Firstly,according to the operation characteristics of elliptic curve scalar multiplication,a hardware multiplexing operation unit that can realize two operations of multiplication and modular inversion is designed to improve the utilization rate of hardware resources,and the Karatsuba-Ofman algorithm is used to improve the calculation performance.Secondly,a fast modular reduction algorithm based on bit reorganization is designed,and a hardware architecture supporting secp256k1,secp256r1 and SCA-256(SM2 standard recommended curve)fast modular reduction calculation is implemented.Finally,the scheduling of modular operations for point addition and point doubling is optimized to improve the utilization of multiplication and fast modular reduction,and reduce the number of cycles required for scalar multiplication calculations.The designed scalar multiplier requires 275 k equivalent gates in 55 nm CMOS technology,the scalar multiplication operation speed is 48 309 times/s,and the area-time product reaches 5.7.
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