基于电压调控自旋轨道矩器件多数决定逻辑门的存内华莱士树乘法器设计
In-memory Wallace Tree Multipliers Based on Majority Gates with Voltage Gated Spin-Orbit Torque Magnetoresistive Random Access Memory Devices
惠亚娟 1李青朕 1王雷敏 1刘成2
作者信息
- 1. 中国地质大学(武汉)自动化学院 武汉 430074;复杂系统先进控制与智能自动化湖北省重点实验室 武汉 430074;地球探测智能化技术教育部工程研究中心 武汉 430074
- 2. 中国科学院计算技术研究所 北京 100080
- 折叠
摘要
在使用新型非易失性存储阵列进行存内计算的研究中,存内乘法器的延迟往往随着位宽的增加呈指数增长,严重影响计算性能.该文设计一种电压调控自旋轨道矩磁随机存储器(VGSOT-MRAM)单元交叉阵列,并提出一种存内华莱士树乘法器的电路设计方法.所提串联存储单元结构通过电阻求和的方式,有效解决磁存储器单元阻值较低的问题;其次提出基于电压调控自旋轨道矩磁存储器单元交叉阵列的存内计算架构,利用在"读"操作期间实现的5输入多数决定逻辑门,进一步降低华莱士树乘法器的逻辑深度.与现有乘法器设计方法相比,所提方法延迟开销从O(n2)降低为O(log2 n),在大位宽时延迟更低.
Abstract
In the research on utilizing emerging non-volatile storage arrays for in-memory computing,the latency of in-memory multipliers often exhibits exponential growth with increasing bit width,and significantly impacts the computational performance.A Voltage-Gated Spin-Orbit Torque Magnetoresistive Random-Acess Memory(VGSOT-MRAM)device unit crossbar array is proposed and a circuit design approach for in-memory Wallace tree multipliers is presented in this paper.The proposed series-connected storage unit structure effectively addresses the issue of low resistance values in magnetic storage units through resistive summing.Furthermore,an in-memory computing architecture based on a voltage-controlled spin-orbit torque magnetic storage unit crossbar array is introduced.Finally,a five-input majority decision logic gate implemented during the"read"operation is leveraged to further reduce the logic depth of the Wallace tree multiplier.Compared to existing multiplier design methods,the proposed approach reduces the delay overhead from O(n2)to O(log2n),with even lower latency for larger bit widths.
关键词
存算一体/新型非易失性存储器/自旋轨道矩磁存储器/华莱士树乘法器Key words
Processing in memory/New non-volatile memory/Spin-Orbit Torque Magnetoresistive Random-Acess Memory(SOT-MRAM)/Wallace tree multiplier引用本文复制引用
出版年
2024
NETL
NSTL
万方数据