In-memory Wallace Tree Multipliers Based on Majority Gates with Voltage Gated Spin-Orbit Torque Magnetoresistive Random Access Memory Devices
In the research on utilizing emerging non-volatile storage arrays for in-memory computing,the latency of in-memory multipliers often exhibits exponential growth with increasing bit width,and significantly impacts the computational performance.A Voltage-Gated Spin-Orbit Torque Magnetoresistive Random-Acess Memory(VGSOT-MRAM)device unit crossbar array is proposed and a circuit design approach for in-memory Wallace tree multipliers is presented in this paper.The proposed series-connected storage unit structure effectively addresses the issue of low resistance values in magnetic storage units through resistive summing.Furthermore,an in-memory computing architecture based on a voltage-controlled spin-orbit torque magnetic storage unit crossbar array is introduced.Finally,a five-input majority decision logic gate implemented during the"read"operation is leveraged to further reduce the logic depth of the Wallace tree multiplier.Compared to existing multiplier design methods,the proposed approach reduces the delay overhead from O(n2)to O(log2n),with even lower latency for larger bit widths.
Processing in memoryNew non-volatile memorySpin-Orbit Torque Magnetoresistive Random-Acess Memory(SOT-MRAM)Wallace tree multiplier