With the advancement of robot automatic navigation technology,software-based path planning algorithms can no longer satisfy the needs in scenarios of many real-time applications.Fast and efficient hardware customization of the algorithm is required to achieve low-latency performance acceleration.In this work,High Level Synthesis(HLS)of classic A* algorithm is studied.Hardware-oriented data structure and function optimization,varying design constraints are explored to pick the right architecture,which is then followed by FPGA synthesis.Experimental results show that,compared to the conventional Register Transfer Level(RTL)method,the HLS-based FPGA implementation of the A* algorithm can achieve better productivity,improved hardware performance and resource utilization efficiency,which demonstrates the advantages of high level synthesis in hardware customization in algorithm-centric applications.
维普
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