A System-level Exploration and Evaluation Simulator for chiplet-based CPU
As Moore's Law comes to an end,it is more and more difficult to improve the chip manufacturing process,and chiplet technology has been widely adopted to improve the chip performance.However,new design parameters introduced into the chiplet architecture pose significant challenges to the computer architecture simulator.To fully support exploration and evaluation of chiplet architecture,System-level Exploration and Evaluation simulator for Chiplet(SEEChiplet),a framework based on gem5 simulator,is developed in this paper.Firstly,three design parameters concerned about chiplet chip design are summarized in this paper,including:(1)chiplet cache system design;(2)Packaging simulation;(3)Interconnection networks between chiplet.Secondly,in view of the above three design parameters,in this paper:(1)a new private last level cache system is designed and implemented to expand the cache system design space;(2)existing gem5 global directory is modified to adapt to new private Last Level Cache(LLC)system;(3)two common packaging methods of chiplet and inter-chiplet network are modeled.Finally,a chiplet-based processor is simulated with PARSEC 3.0 benchmark program running on it,which proves that SEEChiplet can explore and evaluate the design space of chiplet.
ChipletDesign space explorationComputer architecture simulatorCache system
万方数据
维普
