首页|基于功率MOS管的板级干扰器设计

基于功率MOS管的板级干扰器设计

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为了解决集成电路抗扰性测试设备占据空间大、存在外部电路元件击穿等安全隐患问题,提出了一种可以对集成电路芯片源端电压进行周期性扰动的板级干扰器.该干扰器以低阻抗MOS管与肖特基二极管串联结构作为输出驱动,通过FPGA来周期性控制MOS管开关,根据相位累加的原理合成出干扰电源信号,且能通过改变FPGA输出频率和反馈电阻大小来实现干扰电源信号频率与幅度的调节.将干扰器接入负载电路进行测试,结果表明:干扰器在 1 MHz~10 MHz与60 MHz~100 MHz频段,对3 Ω,50 pF负载的电源端扰动幅值达到0.6 V以上,驱动能力理想.因此该干扰器适合作为干扰信号源应用于实际的芯片电源端在 1 MHz~10 MHz与 60 MHz~100 MHz频段的电磁干扰测试实验;相比较于现有的设备,其具有结构简单、低功耗、大驱动、成本低、安全方便等优点.
Design of Compact Large Driving Period Board-Level Interference Generator Based on MOSFET
To solve the problems of large space occupying of the integrated circuit immunity test equipment and breakdown of external circuit components,a kind of board-level jammer which can periodically disturb the source voltage of integrated circuit chip is proposed.The jammer is driven by the series structure of low impedance MOSFET and Schottky diode.The MOSFET switch is controlled periodi-cally by FPGA,and the jamming power signal is synthesized according to the principle of phase accumulation.The frequency and ampli-tude of the jamming power signal can be adjusted by changing the output frequency and feedback resistance of FPGA.The results show that in 1 MHz-10 MHz and 60 MHz-100 MHz bands,the disturbance amplitude of the jammer to the power source of 3 Ω,50 pF load reaches above 0.6 V,and the driving ability is ideal.Therefore,the jammer is suitable for the electromagnetic interference test as the source of interference signal.Compared with the existing equipment,it has the advantages of simple structure,low power consumption,large drive,low cost,safety and convenience.

integrated circuitselectromagnetic interferencetest equipmentinterference signal sourcelarge drive

金大君、林喏、粟涛

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中山大学电子与信息工程学院,广东 广州 510006

集成电路 电磁干扰 测试设备 干扰信号源 大驱动

广东省基础与应用基础研究项目

2021A1515011922

2024

电子器件
东南大学

电子器件

CSTPCD
影响因子:0.569
ISSN:1005-9490
年,卷(期):2024.47(1)
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