Duty Cycle Correction Circuit Design for High Performance Delay-Locked Loop
A duty cycle correction circuit(DCC)is designed for high performance delay-locked loop(DLL).The duty cycle correction cir-cuit designed is mainly composed of differential amplifier circuit,duty cycle adjustment circuit,buffer circuit and duty cycle detection cir-cuit.Using TSMC 40 nm CMOS process,this circuit is designed and simulated under 1.1 V power supply voltage.The simulation results show that the input clock signal with a frequency of 2 GHz-8 GHz and duty cycle range of 20%-80%can be adjusted into an output clock signal with duty cycle of 50%±0.2%by the duty cycle correction circuit.It can be applied to high performance delay-locked loop.
duty cycle correction circuitduty cycle detectionduty cycle adjustmentdelay-locked loophigh frequency wide range
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