Design of DDR3 SDRAM Fault Simulation IP Core Based on Veloce Emulator
DDR3 SDRAM is widely used in high security fields.In order to evaluate the impact of its fault on the system,a fault simulation IP core is designed based on the Veloce hardware emulator to evaluate the fault response of the memory in the early stage of system design.A fault generation module based on Tcl script and BackDoor technology is developed,which can simulate the soft and hard faults of memo-ry devices.Tk toolbox is used to integrate the operation process and provide a GUI operation interface,which can set the timing and fault point of the fault.Experiment shows that the design can simulate soft and hard errors of this kind of memory in the Veloce emulator.
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