A Design of Low Power Consumption Divider for RF PLL
A programmable frequency divider for high-performance RF phase-locked loops is designed.The frequency divider is formed by cascading seven 2/3 pre-scalers and 8-digit programmable counter,and the D flip-flop in each pre-scaler adopts a clock controlled CMOS(C2 MOS)latch structure,which can finally realize 2-255 frequency division.The frequency divider is realized by adopting TSMC 22 nm CMOS process,and the whole circuit works in the 0.8 V voltage domain.The simulation results show that 2～255 frequency divi-sion can be realized when the clock signal of 10 GHz is input,and the power consumption of the maximum frequency division is only 0.349 mW.The chip can be used for high performance RF phase-locked loop.
low power consumptionprogrammable frequency dividerclock controlled CMOS2/3 pre-scalerD flip flop
万方数据
维普
