Research and Design of RISC-V Processor for Edge Nodes
As a basic component of distributed computing system,edge nodes are sensitive to the cost and power consumption of proces-sors due to limited energy in some work scenarios.A low-power SparrowRV processor based on RISC-V architecture is designed for the special working conditions of edge nodes.SparrowRV adopts Harvard structure,and instruction bus and data bus are separated.It sup-ports RV32IMZicsr instruction set and 2-level pipelined architecture.In order to improve the efficiency of division,a dynamic iterative algorithm based on the division of recovery remainder is proposed,which reduces the number of iterations of division.The processor uses iverilog for function simulation and the function of RV32IMZicsr instruction is verified to be correct.Prototype verification is completed on XC7K325T FPGA for the processor,and the score of Coremark reachs 2.78 CoreMark/MHz.Compared with Tinyriscv and Humming-bird E203,the SparrowRV core improves the same frequency performance by 15.8%and 29.9%,and reduces the dynamic power con-sumption by 4.9%and 32.6%.
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