复数乘法器是快速傅里叶变换(Fast Fourier Transform,FFT)处理器重要的组成部分,用于完成旋转因子的复数乘法运算.由于正则有符号数(Canonical Signed Digit,CSD)复数乘法器结构简单且无需任何只读存储单元(Read Only Memory,ROM)对旋转因子系数进行存储,因此常被用于低硬件开销FFT处理器的实现.为了进一步减少CSD复数乘法器在FFT处理器硬件资源消耗中的占比,提出了一种优化设计方案.此方案通过添加必要的逻辑电路,提前计算系统时钟对CSD复数乘法器的控制逻辑,达到更加有效地控制其所消耗硬件资源的目的.QUARTUS PRIME平台的综合结果显示,在实现 64 点FFT处理器时,至少能够节约逻辑单元(Logic Elements,LEs)使用量 26%,工作频率为 30 MHz时,动态功耗仅为 11.61 mW.
An Optimized Design of CSD Complex Multiplier for FFT Processor
Complex multiplier is important part of FFT processor,which is used to achieve the multiplications of twiddle factors.Since CSD complex multiplier has simple structure and simultaneously requires no ROM for storing the coefficients of twiddle factors,it can be usually used to realize low hardware-cost FFT processor.For further reducing the proportion of CSD complex multiplier in hardware cost of FFT processor,an optimized scheme is proposed.In this scheme,the control logic of CSD complex multiplier is pre-calculated through adding the necessary logic circuit in order to reduce hardware cost efficiently.The compilation reports based on QUARTUS PRIME show that the amount of logic elements used can by saved by 26%and the dynamic power consumption is only 11.61 mW at 30 MHz when a 64-point FFT processor is implemented.
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