A 40 Gbit/s PAM4 Clock Data Recovery Circuit with Adaptive PD_V2I Module
In order to alleviate the jitter introduced by the nonlinearity of the traditional Bang-Bang four-pulse amplitude modulation(PAM4)clock data recovery(CDR)circuit after locking,an adaptive PD_V2I module is proposed.Under the quarter rate architecture,by summing the 9 sets of phase detection information output in parallel by the data edge sampling module,the multi-level current is dynami-cally output,and the current is increased in the unlocked phase to speed up the locking speed;the current is reduced in the locked phase to reduce jitter.The circuit is designed in 40 nm CMOS process.The simulation results show that the four-pulse amplitude modulation clock data recovery circuit works at a serial data rate of 40 Gbit/s,and the peak-to-peak jitter of the recovered clock is 1.1 ps.Compared with the traditional four-pulse amplitude modulation clock data recovery circuit,it has the advantages of fast locking and small jitter.
four-pulse amplitude modulationclock data recoveryquarter ratephase lock loopadaptive
万方数据
维普
