NWell region planning with real-time segmentation for analog layout
In the back-end layout design of analog circuits,reasonable planning of NWell regions plays a crucial role in achieving compactness of placement and routing.To address the challenge of NWell region planning in the analog layout,this paper proposes an NWell region planning framework based on a real-time segmentation algorithm.By utilizing a WellSegNet-well region segmentation network,the initial constraint region of the NWell is generated for the mock self-constructed analog layout dataset,which effectively overcomes the problem of insufficient layout samples.A precise programming algorithm is proposed to operate in the constrained region,so that the generated Nwell could follow the process design rules and obtain the NWell region with usable circuit performance.A set of evaluation criteria is proposed to assess the quality of the generated NWell region.The experimental results show that the proposed algorithm can produce the NWell regions close to the manual layout.Compared with the benchmark algorithm,it achieves a 13%increase in the SSIM index and a 16%increase in the IoU index.It provides an effective approach to the NWell region planning problem in the back-end layout design of analog circuits.
analog ICEDAreal-time semantic segmentationcomputer vision
万方数据
维普
