Research on junction-to-case thermal resistance and package reliability of SOP8 power MOSFET
A chip packaging model was established to investigate the thermal resistance and package reliability of SOP8 dual MOS chip. By using finite element software, the thermal resistance of the chip crust under two plastic packaging materials, namely EME-E115 and CEL-1702HF, was simulated by constructing thermal structure module, and the main heat transfer paths in the chip were analyzed. The deformation and stress of the outer shell, MOSFET and lead frame were compared and analyzed under two types of plastic packaging simulation. The thickness variation of bonding solder was studied to understand its effect on the maximum equivalent stress of MOSFET. The results show that the heat transfer is mainly along the lead frame substrate to the bottom of the plastic-packaging material in the SOP8 dual MOS chip. After thickening the solder to 50 μm, the junction temperature variation of the MOSFET does not exceed 0. 1℃, and the thermal resistance from the junction to the central bottom surface of the plastic packaging material increases by about 1. 3℃·W-1 . Compared with EME-E115, CEL-1702HF can reduce the thermal resistance of MOSFET by about 20％according to simulation. The chip packaging has obvious advantages to resist deformation and stress. Thicker bonding solder can effectively reduce the stress of MOSFET. The maximum equivalent stress of the MOSFET under the plastic package of EME-E115 and CEL-1702HF is shown to rise when the thickness of bonding solder exceeds 40 μm and 50 μm respectively.
万方数据
维普
