Dual-gate superjunction LDMOS with step-doped buffer layer
The structure of super-junction lateral double-diffused metal-oxide-semiconductor(SJ-LDMOS)field-effect transistor with an N-type buffer layer can effectively suppress the substrate-assisted depletion(SAD)effect in traditional structures.To further optimize device performance,a dual-gate silicon-on-insulator(SOI)-based SJ-LDMOS(DG SDB SJ-LDMOS)device structure was proposed with a step-doped buffer layer.The device contains not only planar gate but also trench gate,which could create two current conduction paths within the device.One path is through the highly doped N-type region in the SJ structure,while the other is through the step-doped buffer layer.Additionally,the stepped doping buffer layer can further improve the surface electric field distribution and enhance the device's breakdown voltage.The dual conduction paths improve the uniformity of forward current in the SJ layer and the stepped doping buffer layer,which could effectively reduce the on-state resistance of the device.The simulation results demonstrate that the proposed device structure can achieve a high breakdown voltage of 394 V,an extremely low specific on-resistance of 10.11 mΩ·cm2,and a resultant FOM value of 15.35 MW/cm2.Additionally,the results represent a significant improvement compared to the SJ-LDMOS devices.With the same drift region length,the breakdown voltage is increased by 47％,and the specific on-resistance is decreased by 64.8％.
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