首页|Ce4+掺杂调节晶格畸变优化Bi4Ti2.95W0.05O12陶瓷的电学性能

Ce4+掺杂调节晶格畸变优化Bi4Ti2.95W0.05O12陶瓷的电学性能

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采用固相反应法成功制备了 Bi4Ti2.95W0.05O12-x%CeO2(掺杂量x=0,0.02,0.05)高温无铅压电陶瓷.研究发现Ce4+掺杂量的变化对陶瓷晶格畸变程度具有调节作用.系统地研究了这种调节作用对陶瓷微观形貌、压电性能和介电性能的影响.XRD和扫描电镜测试结果表明,适量的Ce4+掺杂能有效地在压电陶瓷内部引发适度的晶格畸变,进而改善了陶瓷的压电和介电性能,同时降低了介电损耗.当掺杂量x为0.02时,样品展现出最佳性能:d33=8 pC/N,Tc=618 ℃,tanδ=0.09%,Qm=3364.
Optimization of electrical properties of Bi4Ti2.95W0.05O12 ceramics by modulation of lattice distortion with Ce4+doping
High-temperature lead-free piezoelectric ceramics of Bi4Ti2.95W0.05O12-x%CeO2(x=0,0.02,0.05)were prepared using the conventional solid-state method.The effects of the modulating the degree of ceramic lattice distortion by varying the amount of Ce4+doping on the microstructure and the piezoelectric and dielectric properties of the ceramics were systematically investigated.The XRD and SEM results showed that an appropriate amount of Ce4+doping induced a suitable degree of lattice distortion in the piezoelectric ceramics,thereby their piezoelectric and dielectric properties were enhanced and dielectric loss was reduced.Notably,at a doping level of x=0.02,the sample exhibited optimal performance,with a d33 of 8 pC/N,Tc of 618 ℃,tanδ of 0.09%,and Qm of 3364.These results strongly suggest that this material has significant potential for high-level sensing applications.

piezoelectric ceramicsdopinglattice distortionelectrical propertiesmicrostructure

强晓永、刘天天、陈涛、陈阳、王松林

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天津科技大学电子信息与自动化学院,天津 300222

压电陶瓷 掺杂 晶格畸变 电学性能 微观结构

2024

电子元件与材料
中国电子学会 中国电子元件行业协会 国营第715厂(成都宏明电子股份有限公司)

电子元件与材料

CSTPCD北大核心
影响因子:0.491
ISSN:1001-2028
年,卷(期):2024.43(10)