A 16-bit Pipelined-SAR ADC with a Gain-enhanced Fully Differential Ring Amplifier
In pipelined-successive approximation register analog-to-digital converter(pipelined-SAR ADC),it is necessary to use large-open-loop gain operational amplifiers to improve the gain accuracy of closed-loop residual amplifications.The proposed ring amplifier uses a gain-enhanced output stage to improve the open-loop gain and stability,achieving an open-loop gain of over 90 dB and significantly reducing the residue gain errors without any calibration techniques,meeting the accuracy requirement of a 16 bit ADC.The ADC is implemented in the 65 nm CMOS process with an active area of 0.256 mm2.At a sampling rate of 25 MS/s and with Nyquist-rate input,the proposed ADC achieves simulated signal-to-noise distortion ratio(SNDR)and spurious free dynamic range(SFDR)of 77.8 dB and 96.8 dB,respectively,with a power consumption of 2.8 mW.The proposed ADC achieves Walden and Schreier figure-of-merit(FoM)of 18.0 fJ/conversion-step and 174.3 dB,respectively.
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