泄漏功耗是集成电路应用中的关键问题,体偏置调节技术是最常用的功耗调节技术之一.传统的体偏置调节电路具有偏置电压范围小、多电源电压等问题,不仅增加了整个系统的成本,还限制了体偏置调节技术的优化效果.基于22 nm FDSOI(Fully Depleted Silicon On Insulator)RVT(Regular Voltage Threshold)工艺,本文提出一种适用于22 nm FDSOI RVT数字集成电路的宽范围体偏置调节电路,该电路具有可编程的(0 V,±2 V)宽电压输出范围,可实现50 mV的偏置电压分辨率,而且不需要额外的电源输入.基于22 nm FDSOI工艺实现了测试电路,仿真结果表明,本文提出的体偏置调节电路可将测试电路的待机泄漏降低34%～92%,并具有较宽的性能跟踪范围.
Wide-range Body Bias Adjustment Circuit Design Based on 22 nm FDSOI RVT Process
Leakage power consumption is a key issue in integrated circuit applications,and body bias adjustment technology is one of the most commonly used power consumption adjustment technologies.The traditional body bias adjustment circuit has problems such as small bias voltage range and multiple power supply voltages,which not only increases the cost of the entire system,but also limits the optimization effect of body bias adjustment technology.Based on the 22 nm FDSOI(Fully Depleted Silicon on Insulator)RVT(Regular Voltage Threshold)process,a wide-range body bias adjustment circuit suitable for 22 nm FDSOI RVT digital integrated circuits is proposed.This circuit has a programmable(0 V,±2 V)wide voltage output range,can achieve 50 mV bias voltage resolution,and does not require additional power input.The test circuit was implemented based on the 22 nm FDSOI process.The simulation results show that the body bias adjustment circuit proposed in this design can reduce the standby leakage of the test circuit by 34%to 92%and has a wide performance tracking range.
22 nm FDSOIbody bias adjustmentleakage powerreverse body bias
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