A convolutional neural network accelerator design scheme based on the ZYNQ platform is proposed to address the issues of large-scale convolutional neural network models and limited computing resources in embedded systems.Adopting the principle of software hardware collaborative design,first,design image and parameter input modules on the FPGA side;Then,using FPGA parallel computing technology to implement convolutional and pooling layer operations,and capturing handwritten digital images and LCD display results through a camera;Finally,implement handwritten digit recognition on an embedded platform.The experimental results show that the computational speed of the convolutional and pooling layers is 2.68 times faster than that of the ARM platform.
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