Parallel optimization of convolution algorithm on multi-core DSP
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原文链接
国家科技期刊平台
NETL
NSTL
维普
万方数据
针对国防科技大学自主研发的异构多核数字信号处理(digital signal processing,DSP)芯片的特征以及卷积算法自身特点,提出了一种面向多核DSP架构的高性能多核并行卷积实现方案.针对1×1 卷积提出了特征图级多核并行方案;针对卷积核大于1 的卷积提出了窗口级多核并行优化设计,同时提出了逐元素向量化计算的核内并行优化实现.实验结果表明,所提并行优化方法实现单核计算效率最高能达到64.95%,在带宽受限情况下,多核并行扩展效率可达到48.36%～88.52%,在典型网络ResNet50 上的执行性能与E5-2640 CPU相比,获得了5.39 倍性能加速.
According to the characteristics of the heterogeneous multi-core DSP(digital signal processing)chip independently developed by National University of Defense Technology and the characteristics of the convolution algorithm,a high-performance multi-core parallel convolution implementation scheme for multi-core DSP architecture was proposed.A feature graph level multi-core parallel scheme is proposed for 1×1 convolution.For convolutions with kernels larger than 1,a window level multi-core parallel optimization design was proposed,and an element-wise vectorization based intra-core parallel optimization implementation was proposed.The experimental results show that the proposed parallel optimization method can reach a maximum single core computing efficiency of 64.95%.When the bandwidth is limited,the parallel expansion efficiency of multi-core can still reach 48.36%～88.52%.Compared with E5-2640 CPU,the execution performance on the typical network ResNet50 achieves 5.39x performance acceleration.
国家科技期刊平台
NSTL
维普
万方数据
