Design of DAC test based on sequential equivalent sampling
With the rapid development of digital-to-analog converters(DAC),high sampling accuracy and high sampling rate cannot be achieved simultaneously in DAC testing.A DAC test design method based on sequential equivalent sampling is proposed to solve the problem of effective resolution deterioration,which caused by noise increase due to sampling rate increase.The method expands the high-frequency original signal in time domain,and samples expanded signal with uniform period.The key is to generate fixed frequency difference between the period of sampling clock and the period of input signal.In addition,this paper analyzes the influence of sampling clock jitter on the effective-number-of-bits(ENOB)of the system,determines the maximum clock jitter of the system,and designs the sampling structure and period of the test system according to the periodic characteristics of the tested signal.A 16 Bit,500 MHz output DAC is tested by this method and the results are compared with traditional method by external spectrometer.The results show that the spectral characteristics obtained in the two experiments are consistent,and the proposed method achieves about 4 dBc improvement in Spurious-free dynamic range(SFDR)and about 3 dBc improvement in Two-tone intermodulation distortion(IMD)parameters,which proves the effectiveness of the sequential equivalent sampling DAC test method.
万方数据
维普
